1. Field of the Invention
The present invention relates to sequence controllers of the digital logical circuit type, in which the desired sequence instruction is read from its sequence program part, and the sequence is processed and controlled in its processing circuit.
2. Description of the Prior Art
Being indispensable in the present-day industrialized society, the sequence control technique is widely used in the field of industrial process control, such as power plant and substation control, conveyor system control, machine tool control, assembly line control in the automotive plant, and rolling line control. For these controls, the contact relay sequence control has long been used. This type of sequence control, however, is inconvenient for applications where design modifications are often made on a control system, resulting in degradation of reliability. Recently, the controlled objectives have become much more sophisticated which has necessitated the use of an increasing number of relays, with the result that the logical design has become intricate and the approach to higher speed control has become more difficult.
One solution to this problem in the prior art is the sequence controller with computer-like control functions adapted to sequence controls, in which a program (i.e., a pattern of sequence control operation) is stored in a core memory by way of the keyboard according to a predetermined specific format, the process state is sampled at certain time intervals and compared with the stored data, and an output is generated according to the result.
This sequence controller operates in general on flow-chart system or Boolean algebraic system (conversion system) through programming. When a relay sequence is programmed for a computer, the necessary logical operation is expressed in terms of Boolean algebra, which is programmed and stored in a core memory of the sequence controller. This Boolean algebraic system offers high processing efficiency.
This programming control will be described by way of example with reference to FIGS. 1 through 3. A sequence diagram as shown in FIG. 1 may be expressed by Boolean algebraic equations as follows. EQU Y.sub.1 = (X.sub.1 + X.sub.3).sup.. X.sub.2 = X.sub.1 .sup.. X.sub.2 + X.sub.3 .sup.. X.sub.2 ( 1) EQU y.sub.2 = x.sub.4 .sup.. x.sub.5 + x.sub.6 ( 2)
where X.sub.1 to X.sub.6 stand for input contacts, among which X.sub., X.sub.3, X.sub.4 and X.sub.5 are make-contacts which close the individual circuits when the coil is excited, and X.sub.2 and X.sub.6 are break-contacts which open the individual circuits when the coil is excited; and Y.sub.1 and Y.sub.2 denote output relays.
FIG. 2 is a block diagram showing a conventional digital logical circuit type sequence controller with functions equivalent to those of the above-mentioned relay sequence circuit. In FIG. 2, X.sub.1, X.sub.2, X.sub.3, . . . denote contacts of external inputs, and the numeral 1 represents an input selection circuit which selects the necessary input contact and supplies datum of the state of the selected input contact to a logical processing circuit 2 which is capable of performing a given sequence processing. The numeral 3 denotes an output control circuit which holds the specific output relays Y.sub.1 and Y.sub.2 in on or off state according to the processed result reached by the processing circuit 2. The numeral 4 represents a sequence program storage circuit which stores sequence programs and reads them in sequence and supplies the read program to the processing circuit 2. An example of this processing circuit is illustrated in block form in FIG. 3, in which FF.sub.1, FF.sub.2 and FF.sub.3 denote flip-flop circuits, AND a logical AND circuit, OR a logical OR circuit, and G.sub.1 to G.sub.5 gates. This circuit performs processing as summarized below in reference to Y.sub.1 as in Eq. (1).
Memory Address Sequence Instruction Processing ______________________________________ 1 LOAD X.sub.1 1 X.sub.1 .fwdarw.FF.sub.1 2 FF.sub.1 .fwdarw.FF.sub.2 3 O.fwdarw.FF.sub.3 2 AND X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 2 FF.sub.1. FF.sub.2 .fwdarw.FF.sub.2 3 OR X.sub.3 1 X.sub.3 .fwdarw.FF.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 3 FF.sub.1 .fwdarw.FF.sub.2 4 AND X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 2 FF.sub.1. FF.sub.2 .fwdarw.FF.sub.2 5 SET Y.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 3 FF.sub.3 .fwdarw.OUT Y.sub.1 ______________________________________ (Note: The numerals 1 , 2 , and 3 indicate the timing sequence for the processing.)
When a sequence instruction LOAD X.sub.1 at memory address 1 is read from a memory in the sequence program storage circuit 4, this instruction is decoded and the state of input contact X.sub.1 is stored in the flip-flop FF.sub.1. Then the gates G.sub.1 and G.sub.3 are opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2, and the binary code "0" is stored as an initial set signal in the flip-flop FF.sub.3. Then, when another sequence instruction AND X.sub.2 at address 2 is read from a memory in the sequence program storage circuit 4, the state of complement X.sub.2 of input contact X.sub.2 is stored in the flip-flop FF.sub.1, and the gate G.sub.2 is opened whereby the flip-flops FF.sub.1 and FF.sub.2 undergo AND logic and the result is stored in the flip-flop FF.sub.2. The state of input contact X.sub.3 is stored in the flip-flop FF.sub.1 by another sequence instruction OR X.sub.3. Then the gate G.sub.4 is opened whereby the flip-flops FF.sub.2 and FF.sub.3 undergo OR logic, and the result is transferred to the flip-flop FF.sub.3. After this step, the gate G.sub.1 is opened whereby the datum stored in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2. When an instruction AND X.sub.2 at address 4 is read, the same processing as performed by the instruction at address 2 is carried out. Then, when an instruction SET Y.sub.1 at address 5 comes in, the gate G.sub.4 is opened whereby the flip-flops FF.sub.2 and FF.sub.3 undergo OR logic, and the result is transferred to the flip-flop FF.sub.3. After this step, the gate G.sub.5 is opened to allow the datum in the flip-flop FF.sub.3 to be delivered to the output relay Y.sub.1 through the output control circuit 3.
Thus, the Boolean algebraic equation, X.sub.1 .sup.. X.sub.2 + X.sub.3 .sup.. X.sub.2 = Y.sub.1, is executed by the sequence instructions at addresses 1 to 5. In the same manner, Boolean algebraic equations expressed by polynomials of AND and OR can be converted into sequence instructions one after another. The sequence instructions are read one after another from the memory of the sequence program storage circuit 4 and executed repeatedly at high speed. Hence the sequence controller shown in FIG. 2 performs functions equivalent to those of the relay sequence shown in FIG. 1. When the relay sequence forms a loop as shown in FIG. 4, this sequence may be expressed in Boolean algebra as follows. EQU Y.sub.1 = X.sub.1 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.3 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.5 X.sub.6 + X.sub.1 .sup.. X.sub.3 .sup.. X.sub.5 .sup.. X.sub.6 ( 3) EQU y.sub.2 = x.sub.4 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.3 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.2 .sup.. x.sub.6 + x.sub.4 .sup.. x.sub.3 .sup.. x.sub.2 .sup.. x.sub.6 ( 4)
because all the loops are to be considered, these Boolean equations are inevitably complicated. If the relay sequence comprises intricate loops, it will become extremely difficult to convert all the logical paths into Boolean equations, and a considerable amount of effort must be made to build a complete sequence program.